In the computing industry, advances in processor technology are continually being achieved. These advances in technology are often expressed in different ways. Clock speed, for example, has often been an indicator of performance. Higher clock speeds contribute to better performance.
Currently, the performance of a processor is often expressed not only in terms of clock speed, but also in terms of the number of available processor cores. For instance, a dual core processor typically has higher performance than a single core processor, even when operating at slower clock speeds.
In the initial development of multi-core processors, the cores (and other components) were connected using conventional bus technology. As the number of cores in a processor increases, however, this approach becomes infeasible and can actually adversely impact the performance of the multi-core processor. As a result, processor designers began considering the concept of an on-chip network. An on-chip network would allow data or packets to be routed more quickly than conventional bus technologies.
Notwithstanding the development of on-chip networks, the performance of a multi-core processor has substantial room for improvement. For example, the routing time of a packet in a conventional multi-core processor depends at least on how many hops the packet is required to make and how long it takes to route the packet at each core. The ability to provide high throughput and low latency routing in an on-chip network is becoming increasingly important, particularly in view of the trends of virtualization, increasing core size, and increasing core number.